This invention relates to semiconductor devices and integrated circuits using sidewall spacer technology.
In order to reduce the electric field in the vicinity of the gate/drain edge of MOSFET devices, it is common to employ a LDD structure which positions a relatively lightly doped region under the gate and a more heavily doped region between the lightly doped region and the field oxide. The processing technology commonly used to realize such LDD structures follows the general prescription of U.S. Pat. No. 4,038,107 granted to G. Mart and G. E. Smith; that is, the principal steps include forming source and drain openings to allow one or more first ion implantation steps; reducing the size of the openings by forming (e.g., by oxidation) spacers on the sidewalls of the gate stack; and then by means of one or more second ion implantation steps, implanting additional impurities through the reduced size openings. The spacer serves to prevent any substantial implantation in the region thereunder, thus preserving the desired lightly-doped region.
Spacer technology has become very common in 1.25 .mu.m and 0.8 .mu.m technology where a quadrant-like spacer typically comprises a single L-shaped base layer adjacent both the gate stack and the substrate and also includes a filler layer disposed between the legs of the L-shaped base layer. For these design rules, use of a single layer grown oxide for the base layer and a deposited oxide for the filler layer has been found to be adequate for many applications. However, as design rules shrink to well below 1 .mu.m (e.g., 0.5 .mu.m or 0.35 .mu.m ), a number of problems arise or are exacerbated: (1) As the spacer gets very thin, the dielectric quality and the Si/SiO.sub.2 interfacial substructure of the spacer material become more and more important. The quality problem is further complicated by the fact that the surface of the sidewalls on which the base layer is formed is typically a polysilicon surface, not a single crystal silicon surface; (2) A well-known micro bird's beak (e.g., feature 10 of FIG. 10) forms at the edges of the gate during the thermal oxidation step used to grow the base layer. The bird's beak itself reduces the localized electric field at the edges of the gate, which is beneficial. However, if the bird's beak is too large, the thickness of the gate oxide may become too nonuniform. Consequently, the threshold voltage characteristics of the FET may be degraded and the source/drain series resistance may increase. Therefore, it would be highly desirable to be able to tailor the bird's beak to different transistor designs so as to improve control over threshold voltage and series resistance; and (3) A significant portion of the spacer may be underdesirably etched away when the wafer is cleaned by wet chemical etching (e.g., before performing a salicide process), resulting in the possible exposure of underlying gate-level defects (GLDs; e.g., Si particles protruding from a polysilicon gate stack). In subsequent processing, a silicide may form on the exposed GLDs and cause device failure or performance degradation. Therefore, protecting the spacer from such etching degradation would be highly desirable.